Prof. Pallav Gupta at Villanova

Refereed Journal Articles PDF Print E-mail
  1. P. Gupta, R. Zhang, and N. K. Jha, Automatic Test Pattern Generation for Combinational Threshold Logic Networks, IEEE Trans. VLSI Syst., 2008, vol. 16, no. 8, pp. 1035-1045, Aug. 2008.
  2. P. Gupta, N. K. Jha, and L. Lingappan, A Test Generation Framework for Quantum Cellular Automata (QCA) Circuits, IEEE Trans. VLSI Syst., vol. 15, no. 1, pp. 24-36, Jan. 2007.
  3. R. Zhang, P. Gupta, and N. K. Jha, Majority and Minority Networks Synthesis with Application to QCA, SET, and TPL Based Nanotechnologies, IEEE Trans. Computer-Aided Design, vol. 26, no. 7, pp. 1233-1245, July 2007.
  4. P. Gupta, A. Agrawal, and N. K. Jha, An Algorithm for Synthesis of Reversible Logic Ciruits, IEEE Trans. Computer-Aided Design, vol. 25, no. 11, pp. 2317-2330, Nov. 2006.
  5. P. Gupta and N. K. Jha, An Algorithm for Nano-pipelining for RTD-based Circuits and Architectures, IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 159-167, Mar. 2005.
  6. R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies, IEEE Trans. Computer-Aided Design, vol. 24, no. 1, pp. 107-118, Jan. 2005, (top 25 most downloaded paper of TCAD).
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